２４ＫＥｃ® ハードＩＰコア

• Hard IP cores allow designers to significantly reduce design time, efficiently use resources, and quickly get to market
• Based on MIPS32 architecture for high performance
• 16KB Instruction and 16KB writeback Data cache for more flexibility and higher performance
• Instruction and data scratchpad interfaces available
• A coprocessor 2 (COP2) interface enables easy coprocessor connection and support
• Extensive clock gating reduces power consumption without reducing application performance
• Enhanced JTAG (EJTAG) debug with trace and fast download enable quick and easy debugging
• All major operating systems and compiler tool chains, and hundreds of third-party development tools, support the MIPS architecture
• Testability features include BIST and full scan
• Supports CorExtend capability which enables users to significantly enhance the value and competitive advantage of their SoC products

ハード・マイクロプロセッサ・コア

• 333 MHz in TSMC .13µm process
• 476 MHz in TSMC 90G process

32ビットMIPS32拡張アーキテクチャ

• 32-bit address and data paths
• Memory management unit with TLB
• Bit field instructions
• Vectored interrupts

メモリ管理ユニット

• 32 dual-entry JTLB

固定キャッシュ

• 16K/16K instruction and data caches
• 4-way set-associative
• Write-back or write-through

整数乗算/除算ユニット

• Fast MDU
• Maximum issue rate of one 32x32 multiply per clock
• Scratchpad Interface

汎用コプロセッサ(COP2)インターフェース

• 32-bit interface to an external coprocessor

電力制御

• Minimum frequency: 0 MHz
• Power-down mode (triggered by WAIT instruction)
• Support for extensive use of local gated clocks

EJTAGデバッグ

• Support for single stepping
• Virtual instruction and data address breakpoints

開発サポート

• MIPS® SDE GNU based toolchain, MIPSsim™ Instruction Set Simulator, MIPS DSP Library. These tools are licensed for Windows, Linux and Solaris operating systems
• A complete offering of third-party development tools

¹ワーストケースの動作周波数 (SS process corner, Vdd nom - 10%, Tj=125 oC) 完全なクロック入力時
²16K/16K キャッシュ